Silicon on insulator (SOI) technology uses a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics. This layered structure reduces parasitic device capacitance, thereby improving performance.
As SOI technology continues to become more pervasive in the microelectronics industry, there is a need for a simple and cost effective way to create a source to body contacted device that has low gate capacitance and small area. Typically, for example, body contacted devices in SOI have large gate capacitance or high variability due to channel width variation. In fact, currently used designs of source to body contacted devices in SOI have added expensive processing steps, parasitic gate area structures (e.g., t-body/h-body/u-body), or structures with high width tolerance (L-body), all of which have drawbacks.